搬回了bbs.lemote.com

flygoat · 发表于 2020-7-10 10:51:05

搬回了bbs.lemote.com的老域名。

现在本站由龙梦双路3A3000+7A服务器以及龙梦Fedora28系统强力驱动！

[root@3B3000 ~]# cat /proc/cpuinfo5 q3 K2 z$ A1 }2 u+ @2 r' y
system type : generic-loongson-machine
$ q9 P: O7 h$ J7 U6 Q
machine : loongson,generic( N2 ]: _- z& O9 t4 Q. V- f
processor : 0% ?0 H& _* Y1 U" X9 E1 A0 v
cpu model : Loongson-3 V0.13 FPU V0.1
% J0 R. a7 ~* f4 b$ e! \
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
. i# o, H6 L" Q# Z" e! D M
CPU MHz : 1450.00( E5 W6 k0 A" Y5 A6 E$ g7 @ s- a5 I
BogoMIPS : 2887.52
! ^# R9 z6 J! m9 ~5 n
wait instruction : yes
6 I1 s6 T. ~' i% S* g- ]6 s
microsecond timers : yes9 X* J& F7 I& H
tlb_entries : 1088
/ r- J: T3 _! K+ { w; V& Y
extra interrupt vector : no
2 m( H2 A$ u9 O: l" j# T/ k
hardware watchpoint : yes, count: 0, address/irw mask: []
% e" z5 r9 t9 z/ X& C/ ?
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2! v" u+ c2 L7 M' I$ H1 C$ t& o Y
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2% ]8 r1 ~; L: _# v
shadow register sets : 1
) q# l! a- } k# w/ ?8 V
kscratch registers : 6
; H( G7 F7 T c" y& J S# E
package : 0+ _8 N; J! ^0 E$ _
core : 0
+ O1 d1 A, a. U
VCED exceptions : not available7 B$ s( S. d' L
VCEI exceptions : not available
3 @+ {7 ~6 `( Q6 W, {
" u5 j& ^( ]! C. @
processor : 1/ J1 K1 @" u2 O( k
cpu model : Loongson-3 V0.13 FPU V0.1
$ P$ T: p5 O2 G0 F7 {' B7 D2 a
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz1 l a+ j4 J* K0 I/ W+ L# S, x0 l! F
CPU MHz : 1450.00: e9 M9 o9 W+ X U$ |6 N8 x0 h
BogoMIPS : 2902.61
7 y) s% V/ N1 U! t
wait instruction : yes
" Y5 J+ ^ D$ ?! N
microsecond timers : yes5 a9 L( J0 g+ K9 I
tlb_entries : 1088$ H9 [/ y/ H6 {1 J* X
extra interrupt vector : no
5 r2 [& [. y( ^
hardware watchpoint : yes, count: 0, address/irw mask: []+ l/ d4 \* e4 P/ m$ ~2 r
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
; U( m% j- L$ K5 ~6 ?& k
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
( d I2 q% p, v( y
shadow register sets : 19 ]; F1 f, g, Z h5 C2 {9 ^
kscratch registers : 6
2 J( F5 R) |9 ?
package : 00 B' g9 F( g3 M% C k9 R( U, m3 \9 Z
core : 1+ D2 K1 | O! N1 i" _" \, f9 N
VCED exceptions : not available
$ |2 S U6 r% ]1 v
VCEI exceptions : not available8 A0 h# ?' W5 _0 ~7 o
$ s4 [( H( r I& W# g! w2 v
processor : 20 B3 N9 B1 w2 r, D
cpu model : Loongson-3 V0.13 FPU V0.1; q$ K) W8 g) ^( @3 W8 O
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
1 f% ?+ _2 o, C6 V
CPU MHz : 1450.00; b9 ` j6 ]6 B5 J& o6 d5 X' |1 }
BogoMIPS : 2902.61, b$ u0 b1 ^+ s w
wait instruction : yes
6 L8 M! t5 d9 K) }- f
microsecond timers : yes
& E) }( P( Q0 w$ ?2 Z; {; D
tlb_entries : 1088
) I# ^4 @+ u: M% d3 Z. w, V" @
extra interrupt vector : no$ k1 p1 @& a# c0 ~' @' V f# |
hardware watchpoint : yes, count: 0, address/irw mask: []" m/ K# }/ [2 O( x R/ z- N
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
; @$ w8 z. ]" \) }3 Y
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2% n2 \4 m2 O1 ]6 W3 F$ m* Z" k
shadow register sets : 1
7 A: ` d7 U5 @. |, t* ^- B
kscratch registers : 6
) o9 i3 Q; j& ~% c$ h: R+ O+ l/ R" @
package : 0# a$ u, F4 Z. S
core : 2
P$ ]3 {) i: K- b
VCED exceptions : not available( b# `& A4 O. v, W6 y2 [. Z5 L
VCEI exceptions : not available
' U" t7 c0 D( E# d7 A
+ l) v4 ]( ? B0 `/ u
processor : 3
' V2 b G2 i; U6 k/ a
cpu model : Loongson-3 V0.13 FPU V0.1: Z/ b, K1 p( F# z& S* ~$ B
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz* ^, x( q' L; W' V; l0 _# t8 M
CPU MHz : 1450.00
+ W/ E9 _- f$ N& x, U0 `
BogoMIPS : 2902.61. s$ E. o+ e" {: R
wait instruction : yes
2 K+ N& k |3 l
microsecond timers : yes
" G" Z3 W- r3 V8 o( ~
tlb_entries : 1088
' b: z/ Q8 M; ^7 v( G
extra interrupt vector : no% ]6 m* ^- h6 h2 m' o% s0 e
hardware watchpoint : yes, count: 0, address/irw mask: []
7 q) m- m6 L7 T, e( a& h' f
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
* K K# m2 \# o$ E7 P* N; m2 i+ A
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
* K- i' |- p, U) y1 [: G
shadow register sets : 1
a) V7 A6 D$ M3 w. \- H7 Y
kscratch registers : 6
9 c: C/ W: L5 N0 r
package : 0: F u6 e% I2 N( u* `# ?
core : 3$ l' s. [/ D$ F5 C
VCED exceptions : not available
7 p1 [" A* l t8 e
VCEI exceptions : not available
% r" U$ G* i" f! A: `
4 Q2 n2 w3 p0 [' e
processor : 4: I* p# b0 m |5 h
cpu model : Loongson-3 V0.13 FPU V0.14 B- ~, ?$ p" l- o: r, [* |1 H
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz- G8 W. |' [5 g1 f1 M) B
CPU MHz : 1450.00! \' m5 O* A* L5 W1 v2 [: ~
BogoMIPS : 2887.52+ A& W; ]3 p4 U$ h) L% N
wait instruction : yes! z1 l$ w9 m7 ^# G& e+ S/ o
microsecond timers : yes
2 A+ K' m1 Y/ Y# o
tlb_entries : 10880 m/ c0 E: k# r+ o
extra interrupt vector : no- y; n2 v$ @4 m" e% R; m9 L- V( p) }
hardware watchpoint : yes, count: 0, address/irw mask: []' r3 J, \. ?3 X w
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
0 L# W# s% z1 h8 |% C+ q
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
: G( t; A" m3 a0 P$ `- D
shadow register sets : 1# \; u* b9 b- ?" y1 x/ Y
kscratch registers : 62 ~1 S9 W0 u; _( F3 M3 e6 z
package : 11 {' t, m/ M8 Y; ]% M; U
core : 0! {4 c1 E. W1 O
VCED exceptions : not available
) x5 p5 ?" m( a
VCEI exceptions : not available: ^: S @5 n) ?& D8 P
/ Y5 J' h$ I& X0 E4 B# H
processor : 56 E0 H$ \+ _" \5 P
cpu model : Loongson-3 V0.13 FPU V0.1
2 G3 V( Q5 |) X4 S4 d
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
1 ?8 W3 E0 S) [" U* [# B8 C+ n
CPU MHz : 1450.00
1 P' t& {1 ~& M4 f% I+ Q
BogoMIPS : 2887.52( \, ?5 b! c& S; L* ?
wait instruction : yes
# q" E, @6 V8 S( V# |. `
microsecond timers : yes& a) M( c, T6 U$ n" p' x
tlb_entries : 1088
* R) J7 E4 B4 I$ g1 ~! u
extra interrupt vector : no7 t/ B: q2 ^& C) H. [! ~' O4 ^
hardware watchpoint : yes, count: 0, address/irw mask: []
9 X* {9 Q' w& m( f+ o, t3 W' Y
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2( K% \" i1 `/ j _0 M# o
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
- j- U F9 ]9 m' O# E% `
shadow register sets : 18 t& s( Q1 {+ E2 F
kscratch registers : 62 h+ e: G5 K. u: y# Z, g
package : 1 z, J ]- E* u5 W F7 o( J
core : 1
3 g. F" f% i$ G$ e/ L
VCED exceptions : not available, m( b. _7 u+ e4 V2 o
VCEI exceptions : not available& k7 z/ ~ {, E+ G+ t' \: Y
% m$ i$ @% D$ f. A: q
processor : 68 i0 X8 P; u9 B1 S6 l
cpu model : Loongson-3 V0.13 FPU V0.1! J7 d: T3 ^% E- b8 @2 C$ r
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
$ i6 N) S% y5 B% M/ g
CPU MHz : 1450.004 G7 i$ Z# b* l1 ?7 o4 d
BogoMIPS : 2887.52, b" {! A# A6 a
wait instruction : yes: f! j7 u! p$ v" S3 S. U
microsecond timers : yes
, G) [0 a0 c$ a) P# n% O; A
tlb_entries : 1088% f6 z4 l& W- t1 z/ E4 L4 T
extra interrupt vector : no+ n+ o- c* x7 x* Z2 i( k% q
hardware watchpoint : yes, count: 0, address/irw mask: []6 A0 L! M' P' P5 D8 p$ v" P
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2, j+ ]3 @5 E1 _6 r, y5 L
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2& Z, g, \1 X5 v d+ [, U
shadow register sets : 1, e$ s, ]$ ~9 d) a% g
kscratch registers : 6) E, P, J/ u$ W
package : 1) ]$ G; ^- D% M& ?1 ?; y! _
core : 22 v1 G: j/ C x
VCED exceptions : not available; [: v' U7 a9 i0 n
VCEI exceptions : not available
/ A+ b; R* ~4 k: b
' Z$ B9 _, D& }0 P' C' y+ j
processor : 7
; e6 v. V( N& g& J8 {
cpu model : Loongson-3 V0.13 FPU V0.1
& H, @/ d/ L) O: s. x
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz. ?! o6 @* R, L$ Y
CPU MHz : 1450.00( f9 v c0 E4 z* ^2 s9 r4 N& l6 ~
BogoMIPS : 2887.52
& D8 U, A0 h9 X, N+ i4 } M
wait instruction : yes3 ?: @4 A9 x' H5 D! z) }! X$ M" I
microsecond timers : yes
" y& ]4 m; _, C2 M. M5 d1 u5 c8 h
tlb_entries : 1088
`! f. I" b( ?# L1 G) l$ j
extra interrupt vector : no
* o; v; H* | G! u. O
hardware watchpoint : yes, count: 0, address/irw mask: []6 Q0 A" U3 W6 C( ?! d4 k' c) E4 \
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
6 m& v5 y, p, F) o1 U
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
* _- a1 F4 f Y9 @+ R% U, ~
shadow register sets : 1( m) y8 X8 l4 B, j
kscratch registers : 6, z6 } O+ C6 ?
package : 1: f8 `$ k7 Y! S0 X& m
core : 3, L- [: G3 P% j6 M R& A, Q) Q
VCED exceptions : not available! E; f @5 C8 m0 j; q. K6 K0 Q ?- L1 P
VCEI exceptions : not available0 {# f- f5 A3 L5 L; {/ P

复制代码

lizi5802 · 发表于 2020-7-10 11:01:48

无产者 · 发表于 2020-7-10 11:02:18

前来支持！

shipujin · 发表于 2020-7-10 11:07:30

前来支持！

weilinfox · 发表于 2020-7-10 11:07:59

顶！

Holoo · 发表于 2020-7-10 23:53:32

lyhdzxf · 发表于 2020-7-11 18:40:29

前来支持

windows1089 · 发表于 2020-7-20 10:10:53

来了！

root · 发表于 2020-7-28 12:54:12

好棒好棒

xmzgtx · 发表于 2020-8-30 10:52:26

支持。

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