搬回了bbs.lemote.com

flygoat · 发表于 2020-7-10 10:51:05

搬回了bbs.lemote.com的老域名。

现在本站由龙梦双路3A3000+7A服务器以及龙梦Fedora28系统强力驱动！

[root@3B3000 ~]# cat /proc/cpuinfo8 v' S: K1 D+ k+ r' i# [7 H
system type : generic-loongson-machine
8 t. R! g7 f4 }. H& |4 Q3 Q
machine : loongson,generic
. a0 J5 b) S) r4 k' z+ r& K4 B
processor : 0. f9 Y0 d5 I7 L& W* E/ @
cpu model : Loongson-3 V0.13 FPU V0.1
& _5 O C( e( D2 b Q3 t
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
7 V& F# F6 g- w. {
CPU MHz : 1450.00( A3 T- J- `5 r6 h' ~
BogoMIPS : 2887.52% x, |" E' M! S. ^6 n& k" V
wait instruction : yes
" X8 G$ M/ a! X/ R+ ?
microsecond timers : yes) ^; b+ U* @4 p& g
tlb_entries : 1088/ K. A$ c9 r; i; h# d
extra interrupt vector : no9 H/ T) `( G3 [$ @2 o. y
hardware watchpoint : yes, count: 0, address/irw mask: []$ z( C+ z# J, ~: Y- m& I
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r20 J9 E6 V7 Y2 R9 G# F/ C
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
$ Z: j0 `7 K8 p) X: B
shadow register sets : 1$ P: h; K+ i/ G) g8 |/ ~3 a" |
kscratch registers : 6
3 k7 Y; X4 b1 O/ n, P- D
package : 0
8 i: K6 o( r3 z; g3 X5 p! k/ k( H
core : 0
8 ^6 @7 T+ m/ c8 o) G$ Q+ z& W
VCED exceptions : not available1 M: R z; S8 P$ q3 U2 o
VCEI exceptions : not available
3 m! a& Q1 E* L4 O5 I* W( Q' T
3 R1 U% l' I$ R( [# q
processor : 13 h& ]" }, `' @* y, }
cpu model : Loongson-3 V0.13 FPU V0.19 V: c& Q7 U, O' ^- K) r$ U
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
1 d0 f2 I9 R& ^% N
CPU MHz : 1450.005 R' F% |" p, w9 ~
BogoMIPS : 2902.61
* c$ J. w2 K z
wait instruction : yes
6 R) u3 [; L6 V; q1 @$ a7 ]
microsecond timers : yes
, f& \9 y9 @7 L. v/ y- p; v
tlb_entries : 1088
* J- m" y [0 L7 n
extra interrupt vector : no k/ ] i# `0 g8 h9 `6 P
hardware watchpoint : yes, count: 0, address/irw mask: []
6 P3 a# ^3 j" m5 B
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 q$ ]2 J# M- F- @+ T6 V2 ] ~
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext26 K, ^1 a! b; l' U9 l/ e& D8 j. A9 U' a$ }
shadow register sets : 1
8 G9 O- a, ~" [0 q4 p% }5 o+ @
kscratch registers : 6) _/ `+ Q0 s: {% J# d% S1 `# ~
package : 0
# |' Y& T$ }4 N k0 R. E* x5 h
core : 1
- W, J* \2 w+ s8 H
VCED exceptions : not available
9 S: a/ M* X% m6 C1 t- \0 y
VCEI exceptions : not available
5 D8 N5 x/ c9 r
" N0 F: W- D+ o- L2 S m/ K$ T
processor : 2
9 H/ Y; T$ v G5 y
cpu model : Loongson-3 V0.13 FPU V0.16 B: R5 L' v+ ~, \9 _( c3 B& b2 D
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz+ R. o2 x O# O7 u
CPU MHz : 1450.00
$ k. n$ X) m8 f& j
BogoMIPS : 2902.61* l# D4 R+ Y% n/ d% u! k( b
wait instruction : yes. n5 U- l2 F7 ]2 |) Q T2 l, P2 {1 S
microsecond timers : yes' I5 w" v T6 v& Q
tlb_entries : 1088
9 ]" O; k C. |( g" g. a9 F% N0 H
extra interrupt vector : no
" `6 D( ]6 p0 W2 a# U% R" Q' W
hardware watchpoint : yes, count: 0, address/irw mask: []
3 ~" B6 i- S- h
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
0 E; l' a# [# ]/ i( A0 t
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
# \5 u, @$ K% i$ W! U2 m D
shadow register sets : 1) t8 _( L" m+ q2 S* B
kscratch registers : 62 W% u8 }( N3 q% ^4 t" e' L+ i
package : 0
& I, x0 \! M6 V2 Q
core : 2+ C; i# Q- u. ~
VCED exceptions : not available
2 ?) ?5 l1 H% v4 D' h3 _
VCEI exceptions : not available
& E0 j6 p5 a2 E& L
8 Q& ]( v- A; T
processor : 3
6 S% b, @3 y4 c7 a& V6 n* g
cpu model : Loongson-3 V0.13 FPU V0.1
& ~3 U) N+ k$ K5 L
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz/ _, y d `" T; M" J* p
CPU MHz : 1450.00# j: q6 }6 {# K0 V* c- L
BogoMIPS : 2902.61# r! O( y2 K2 c
wait instruction : yes
# C8 n, W G# x/ p
microsecond timers : yes
& O8 K& p/ w& S, p' v
tlb_entries : 1088
8 C: K- r7 h; x& s+ L
extra interrupt vector : no/ f& Q6 K" F6 f) I+ [
hardware watchpoint : yes, count: 0, address/irw mask: []3 ^2 l7 b' v/ P+ ?4 }' u9 c
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2) P( z- m( Q: J
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
$ N' a8 l* @: Z- a7 |4 k
shadow register sets : 16 {: s* f1 Z2 G0 q
kscratch registers : 6
% v; B; G$ `9 d1 F% D6 S& O! p
package : 0
0 @/ C6 ?7 e, k, F& r
core : 3% ^: I9 \4 Y1 t1 O' I
VCED exceptions : not available; n7 h, K i6 i! a0 T
VCEI exceptions : not available8 X6 ^( G5 E, f/ } |
4 O/ n q {1 x9 Q
processor : 4
! _. j b& b% f7 C! `2 B' L h
cpu model : Loongson-3 V0.13 FPU V0.1
# d/ o5 v, e+ k, g3 n
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
2 ]+ j( U1 Y' n- ^. S$ a/ p
CPU MHz : 1450.00* z; O6 v: k% S% X" g- o* }8 V) p
BogoMIPS : 2887.52
5 n& n+ j( z" R W r, H3 Y: ?4 {
wait instruction : yes
1 n5 s5 N# |8 B) T" C% x& c* n
microsecond timers : yes2 B. e. s( B5 `1 Q+ A r
tlb_entries : 1088) y) {8 C, f+ ]% |- W ^4 ^
extra interrupt vector : no
# y! r6 f0 M. L3 f1 `% Q* w* V( m
hardware watchpoint : yes, count: 0, address/irw mask: []
9 { R( a' _! @* J* d9 `5 L; \
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
* H' c: G% r8 R
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
: b" X. a: Y6 j8 s3 k
shadow register sets : 1
3 |. @$ c9 }' z+ A w! p
kscratch registers : 6
" f" ~" I. h5 v6 A: ~! s
package : 1 \( Q6 M6 u5 ^5 O) m4 b$ R
core : 0
2 U+ [3 `) c. W' q! ~& C# O# `9 d5 i; F
VCED exceptions : not available
4 M) n. m; ] _9 g: l; y4 x
VCEI exceptions : not available
7 s; x5 h4 _9 K3 s1 h$ A" K
' G3 y1 ]0 p+ P& ~0 n/ r7 C
processor : 5
$ q4 B& [- f9 r+ }; G/ ?
cpu model : Loongson-3 V0.13 FPU V0.1
2 j# D: n! a8 ^ V% ^% B
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
L# M I; {" M! G5 G
CPU MHz : 1450.00
BogoMIPS : 2887.52
6 m& c' h+ a- T' p4 w
wait instruction : yes& T/ n8 a" }* \+ g/ ]
microsecond timers : yes6 o+ c6 t3 x! V5 ?1 m* U
tlb_entries : 10888 E4 y/ O/ J9 x) R# M
extra interrupt vector : no' q! w0 ?; j# }& D. n# D, `
hardware watchpoint : yes, count: 0, address/irw mask: []9 P( p( ^; Z& ~% I( _, c' `3 N* i4 c
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
% S ~. E6 _2 Y* B4 ^
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2" C5 ^; I, ]. X/ H& l
shadow register sets : 18 Z) `6 W# p; P. }. p7 M; l9 K
kscratch registers : 6
# P# k1 |* f$ h* j
package : 13 p% i1 h' k: h6 X
core : 1
# K \5 W* d+ s+ y. V
VCED exceptions : not available: `( O8 |3 [- K
VCEI exceptions : not available, R! G" P- [& ^0 k! m" n! _
2 }* f/ e8 e5 y6 b- A
processor : 64 {7 |! W# J$ Q: s2 Q" b9 [9 N0 y
cpu model : Loongson-3 V0.13 FPU V0.1
/ d2 r0 q+ S* V1 T* M. P A
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz2 E+ d" b) B8 f
CPU MHz : 1450.00- |, U M7 g) u1 f, M
BogoMIPS : 2887.52
! K) T/ @8 ]! S8 B
wait instruction : yes
+ R+ H1 l! J: X2 u3 Q6 H
microsecond timers : yes. X1 j1 B: d7 g4 b: S
tlb_entries : 10880 w/ o& G1 E# V4 F
extra interrupt vector : no) f, a) W4 Z3 {! k+ e+ B$ i1 k4 a0 x
hardware watchpoint : yes, count: 0, address/irw mask: []
! J) t) F1 ^8 N- R: D
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2) @; Z g) } @5 V1 ^% Y: V
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2, |7 l( S# J7 X* e. U3 ]
shadow register sets : 1
/ I) G. p! S& p5 D1 }) z b* v
kscratch registers : 6
1 e* F5 k+ t9 z- d( u! e! M
package : 1. M5 L }4 x' q. H3 Q( n, p( j
core : 27 \1 u" ~- Q& v* \- G+ E8 N
VCED exceptions : not available$ c+ l( G5 _ T W/ P4 Q+ { c
VCEI exceptions : not available
% f+ V: O3 `+ d% d9 v
2 i# Q E% I5 v* c7 |
processor : 7
$ t7 U; M& Q$ G8 P$ V& d" I
cpu model : Loongson-3 V0.13 FPU V0.1
5 q5 Y x5 r" f# _& ?( t
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
$ o" o. H0 X- [5 X' ? l8 j
CPU MHz : 1450.00
: G" t6 K1 y8 a/ L/ q+ ^
BogoMIPS : 2887.52* }; |0 y- h+ `
wait instruction : yes
2 h* W# i- D! T/ g( V' ?3 W- G
microsecond timers : yes% v* A! i& {5 l
tlb_entries : 1088! C! v$ I# Y" _+ k
extra interrupt vector : no
4 P% {& ^* Z+ D+ A4 X" A& b* @: h/ p
hardware watchpoint : yes, count: 0, address/irw mask: []
4 l1 i4 ?& [- p3 w: F% ~; Z
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2- [7 ^" w `' V' t; j9 i# M- f
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2) {, B$ P4 ^! K5 Q- l/ T
shadow register sets : 17 \8 L- n# Z1 N) Q( y9 L+ n0 O& Q
kscratch registers : 6 F6 A( H0 b0 \
package : 1
7 y, }7 D9 Q0 i6 X
core : 3; x# \3 C* _# e [
VCED exceptions : not available
% O2 g* O# u' _
VCEI exceptions : not available5 D- d) z Y y- A4 m

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lizi5802 · 发表于 2020-7-10 11:01:48

无产者 · 发表于 2020-7-10 11:02:18

前来支持！

shipujin · 发表于 2020-7-10 11:07:30

前来支持！

weilinfox · 发表于 2020-7-10 11:07:59

顶！

Holoo · 发表于 2020-7-10 23:53:32

lyhdzxf · 发表于 2020-7-11 18:40:29

前来支持

windows1089 · 发表于 2020-7-20 10:10:53

来了！

root · 发表于 2020-7-28 12:54:12

好棒好棒

xmzgtx · 发表于 2020-8-30 10:52:26

支持。

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