搬回了bbs.lemote.com

flygoat · 发表于 2020-7-10 10:51:05

搬回了bbs.lemote.com的老域名。

现在本站由龙梦双路3A3000+7A服务器以及龙梦Fedora28系统强力驱动！

[root@3B3000 ~]# cat /proc/cpuinfo
, c$ k( g, r' x/ R% e
system type : generic-loongson-machine9 F( j& F, q7 } G/ i5 o
machine : loongson,generic7 }, [3 ]& h* v% W7 @' N
processor : 02 |9 ^" B$ {& B0 V
cpu model : Loongson-3 V0.13 FPU V0.1
% C! e1 e$ Z: x- P
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz
5 Q) f+ r0 s; h' S. U8 J: @; b
CPU MHz : 1450.00
0 n8 U( K. ]( B$ f& ?% ]7 P9 x
BogoMIPS : 2887.52
* _8 V( s* G- j3 i7 h' ^! B6 A2 K
wait instruction : yes8 c7 Q3 S4 I+ w: D, H
microsecond timers : yes
; |" i+ A& k# Y/ \# u0 P$ Z
tlb_entries : 1088
( o. X2 i y. U8 X
extra interrupt vector : no
* g( D+ q2 |% z# l; w j1 M5 f
hardware watchpoint : yes, count: 0, address/irw mask: []
: X' {3 [. v$ y
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
2 b+ W4 G1 `7 ?% l
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
: O1 }& y2 D7 A- p* M
shadow register sets : 1
) `% p: C r s! ~) V, O2 {8 z
kscratch registers : 6
4 `% |7 L. b- {' q6 Q0 [& ^
package : 0
- w* u7 v \$ D
core : 0
# P0 ?6 A/ }, {9 E
VCED exceptions : not available0 w. y5 F' ~# k) j3 I* g! F3 }' b; m
VCEI exceptions : not available
" H+ a5 R- Z* ^$ |
- t% s) N! ?$ x, B. W! ^
processor : 1& u* L% o, T# ^. Q% J
cpu model : Loongson-3 V0.13 FPU V0.18 F5 M1 [8 \" ^3 H2 D' n
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz1 [7 L9 O$ }8 V) [: n/ S' g
CPU MHz : 1450.00
, [& D1 V, I8 }" }% \2 `: W( f: C
BogoMIPS : 2902.61 Q8 s( R7 b N3 h
wait instruction : yes+ h9 n- E' R* j2 L4 E
microsecond timers : yes* z) B( D; {4 g; h2 y& C6 t
tlb_entries : 1088
7 Y6 K, C: J- T7 n2 ? H
extra interrupt vector : no
# ]( N4 J* \+ e6 [2 w/ H
hardware watchpoint : yes, count: 0, address/irw mask: []% C, j% A. J& [9 Y
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
) Z8 k. E+ b: ~, a! q! S0 H
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
" E+ r& ~8 e O+ W5 Z1 _
shadow register sets : 1
+ {5 p, G# i1 p" \: S. A
kscratch registers : 6
( ~* ^& g& P! x% ?' _ b" l
package : 0
2 ]. D# r3 C7 G* [) l6 r. c
core : 1
4 y* z. w- t% \& D
VCED exceptions : not available
1 P. l' k! y( b# E8 V
VCEI exceptions : not available* U/ _7 u' a1 {+ n* @2 t. F
6 ?' r. j- \- p5 z
processor : 2& s5 e+ l; V1 [6 R/ y$ h. H
cpu model : Loongson-3 V0.13 FPU V0.14 P3 [ }; s7 K6 l" Y
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz# S* `* d4 A6 W" {) ]. @) c
CPU MHz : 1450.001 d; N$ Z6 C5 p
BogoMIPS : 2902.61
/ Y+ v Q4 y9 o) e: D3 G+ g
wait instruction : yes
# e% j& @- o' w5 O! W0 M
microsecond timers : yes7 P, X2 w0 X N5 Z
tlb_entries : 1088; C+ X" y4 o$ M
extra interrupt vector : no
) w. M! H& K# v! `
hardware watchpoint : yes, count: 0, address/irw mask: []' S% x1 }+ J# n3 k+ F
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
- S6 N) o+ q. h+ P) g% Y4 B) Z/ U
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
5 h/ L* R2 d: b) ~' ^7 J
shadow register sets : 1/ x/ N5 b; C# e6 D- a
kscratch registers : 68 a% E8 B: a: R& c
package : 0: j, q% Y- `! l5 [9 M
core : 2
! R0 E& e* K2 ?" C" x# c7 Y
VCED exceptions : not available
9 f7 { c; a+ K- G. |, C8 B
VCEI exceptions : not available
% n# S0 D; M8 `6 q* A
& W( e6 k* V' X$ \
processor : 3. H3 |" h1 u1 q
cpu model : Loongson-3 V0.13 FPU V0.1
8 }. N- S! l" _
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz8 s# l( J' B$ Y9 G3 k" D
CPU MHz : 1450.00
! Z. G7 H: ?1 h; b/ a3 i
BogoMIPS : 2902.61% Z$ n! E o2 R9 l! h3 q3 i
wait instruction : yes& a, i8 I9 M7 c/ `: e5 Y
microsecond timers : yes
7 ]1 a. i9 o( y. W2 J
tlb_entries : 1088; ~4 ?1 t" T' M& E
extra interrupt vector : no7 o$ c* m/ v9 y3 ~3 b+ q) F" D& i
hardware watchpoint : yes, count: 0, address/irw mask: []( W6 \ J' A+ a6 h- ^
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2( v4 y/ F; S8 Q
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2+ O1 l5 S' |' S; |& c7 I" I: \4 f0 n2 q. I
shadow register sets : 1
/ {0 t4 M. K0 F/ ?( o
kscratch registers : 6
/ J: U( T( {! e0 n
package : 0! p, o* u$ | ]) e7 [. g& i- Z. |
core : 3
T; F2 ]' O9 n, P, s5 ]
VCED exceptions : not available8 o7 V& g( J2 M" P1 V
VCEI exceptions : not available( I% `4 J% |/ a5 y1 Y R
; h6 D' E" K6 b9 v+ ~
processor : 4, D3 `% \- j* z( t- `# A
cpu model : Loongson-3 V0.13 FPU V0.1
: {* }4 Q& A- D$ u" A
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz& r& L$ J" f/ E6 \1 R) {; \ ~
CPU MHz : 1450.00
9 Q; r2 D# H) K& i9 f# g& ^+ J- r6 {
BogoMIPS : 2887.523 o* ^ K" p7 Q6 r
wait instruction : yes0 R5 @/ w2 C% V! l
microsecond timers : yes& I7 n9 W8 ]6 v4 Z! I
tlb_entries : 10885 a& |0 F7 a" I; n- O
extra interrupt vector : no
# J! Q# f/ x2 p }
hardware watchpoint : yes, count: 0, address/irw mask: [], R# @. v+ W+ H) {2 |+ u2 D
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2/ t1 G/ I+ C) ~7 k6 g1 |! }) Z* A
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2# v5 ]# D5 G1 q5 w6 @4 s# x
shadow register sets : 1: {& k! A6 A1 k8 L5 A7 E1 I( G/ @
kscratch registers : 62 g6 O& F% g1 ?$ d
package : 1- o9 o- M& }/ m9 T. K$ m: p
core : 0
3 r3 l- k, O, {) v: Q: s
VCED exceptions : not available
' ]2 H; N: L5 I
VCEI exceptions : not available
0 _" m5 e( k6 f3 @, Z& h$ N
. V( c3 O3 h- g, O9 t4 H
processor : 5
4 m6 w1 z0 M- t. B: E O
cpu model : Loongson-3 V0.13 FPU V0.10 m+ ?7 ~+ F3 f
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz4 X% i2 M$ W; J n$ A7 `$ R
CPU MHz : 1450.000 d/ }8 Y1 q+ C7 n
BogoMIPS : 2887.52
/ I2 k! E; F$ [* q
wait instruction : yes( V- X: C- o8 o8 n$ o
microsecond timers : yes+ W }7 `( T; w1 f/ {7 T9 X
tlb_entries : 1088
extra interrupt vector : no; X( ?; ?$ i a. v$ D: S. J/ E
hardware watchpoint : yes, count: 0, address/irw mask: []7 O- c" K' s& p0 h
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r29 L, _7 D) r3 d
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2, B* a& U3 S7 Z- ^: M* J5 v
shadow register sets : 1
, k$ R" G* P! { @
kscratch registers : 6
; `# v/ t1 r, A
package : 1, H& @! S# B( m/ H# G1 h
core : 1- X! k% x+ m0 M/ a% Y
VCED exceptions : not available1 m, g" N! B! Q0 t
VCEI exceptions : not available6 a% s6 v. t: @% `# _& C
: V' C5 j7 C1 V6 i9 h9 l. Q
processor : 69 q9 u3 @# h7 \
cpu model : Loongson-3 V0.13 FPU V0.13 k, v& Y0 k" {1 [
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz( f+ w! ?7 w1 \3 h, K+ K
CPU MHz : 1450.00
" P8 ?. |; ?3 G; e P. f1 Y
BogoMIPS : 2887.52
9 s8 q' V$ E1 c {* J/ C
wait instruction : yes
# f) D: d5 M' T
microsecond timers : yes
8 Z4 X& _4 y" Z( d3 \3 H7 c
tlb_entries : 1088 A; [+ {0 c4 ~2 Q8 A9 W
extra interrupt vector : no% h2 V! b* l& {9 a; L
hardware watchpoint : yes, count: 0, address/irw mask: []7 J- {$ l y" ~. P9 ^1 x
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
8 R* G+ ? P1 {/ y6 @& |
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2* K a3 T4 m* M9 P
shadow register sets : 1+ x" U a% l5 d+ D; U N3 l
kscratch registers : 6
0 J" ?/ ?! }- K9 N0 c; U) u
package : 1; J* @7 P- l2 L3 K4 _5 ^/ p
core : 2/ C/ k# g% e( i$ @4 ?
VCED exceptions : not available
6 d/ `, w4 z$ x1 {4 y0 G% e- i8 h
VCEI exceptions : not available1 P2 ?0 N$ r9 h7 K( C X
( F1 U) Y1 J2 d; { ~1 U
processor : 7
/ f2 Z, b/ ~+ R T8 P
cpu model : Loongson-3 V0.13 FPU V0.1
3 o% }+ z) p/ ]% p( p+ M( {) d
model name : Loongson-3A R3 (Loongson-3B3000) @ 1450MHz- |" V$ E( R; u- c8 E e4 X
CPU MHz : 1450.00
+ k$ L" Z9 X( Y; e- y% \. K6 v: L* c
BogoMIPS : 2887.52/ W: B% [. H% o0 p) Z- {
wait instruction : yes
/ {6 S4 R/ g$ r' |0 E
microsecond timers : yes7 L. m' d3 w1 x3 ~, `8 P7 b1 C& ~
tlb_entries : 1088
7 Z* I4 O! s7 g7 W6 @& o
extra interrupt vector : no
0 _" o+ O5 Y' H8 V& P$ i8 Y
hardware watchpoint : yes, count: 0, address/irw mask: [] R: _( k2 p6 v* R( s9 M- a
isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2
+ |" f6 D8 X9 u3 Y$ {2 v0 Z
ASEs implemented : dsp dsp2 loongson-mmi loongson-cam loongson-ext loongson-ext2
( q2 ^1 a: n: ]% N0 Y9 W% w/ w
shadow register sets : 1
( ?- C% k2 Q+ s ~" N9 V* j
kscratch registers : 69 a! V+ B+ x# i0 g k
package : 1
, P2 c2 r9 c# z
core : 3
- {) d4 _# G* L! @/ f
VCED exceptions : not available" o3 t& K. M& s. ^# \ D
VCEI exceptions : not available
6 `8 T5 x2 F! y: x/ C6 R T

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lizi5802 · 发表于 2020-7-10 11:01:48

无产者 · 发表于 2020-7-10 11:02:18

前来支持！

shipujin · 发表于 2020-7-10 11:07:30

前来支持！

weilinfox · 发表于 2020-7-10 11:07:59

顶！

Holoo · 发表于 2020-7-10 23:53:32

lyhdzxf · 发表于 2020-7-11 18:40:29

前来支持

windows1089 · 发表于 2020-7-20 10:10:53

来了！

root · 发表于 2020-7-28 12:54:12

好棒好棒

xmzgtx · 发表于 2020-8-30 10:52:26

支持。

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